Custom IC

Kaben is available to undertake custom design services delivering either a standalone IC or simply an IP block.

Kaben works with companies having a high level of expertise in module development, to move designs to a new level of integration. Together, we leverage our partners application experience with our IC design expertise, to deliver market winning solutions.

The latest innovations in SoC design require an extensive library of IP to minimize technical risk, and avoid legal infringement. Kaben has proven analog, digital, and mixed-signal IP blocks, and customizes them for each application to provide a smooth delivery of our customer’s chip. Our System architects work seamlessly with your engineers to create highly differentiated solutions that simplify complicated designs. Our competence ranges from systems architecture to circuit design, Verilog, RTL, digital synthesis, circuit verification, physical implementation and electro-migration, to deliver reliable products to market.

Whether working in an IP delivery mode, or as a business providing full Turnkey chips, Kaben staff can hand off the designs at various stages of development, complementing the customer’s in-house expertise.

Kaben’s R&D Flow was formulated with client and/or cross-functional group involvement in mind. This flow is shown below and a rigorous process is associated with each milestone.

  • Kick-off and Specifications
    • Face to Face kick-off meeting used to discuss and understand the specification with the engineering teams.
  • Datasheet Design Review
    • This document comprises  the specifications in the form of a Datasheet or Preliminary Engineering Document and is reviewed by all parties. Key information includes (as an example) boundary definition and interface specifications such as loading contexts, propagation delays and setup/hold times between domains.
  • Datasheet/Specification/Engineering Document Sign Off
    • Both parties have reviewed, understand and agree upon the target specifications and any cross-functional deliverables.
  • System Study
    • The upfront feasibility effort generally needed in all R&D projects that
      • identify potential issues and works towards a path to resolving them
      • solidifies the architecture to be undertaken and defines the top level
      • Quick turn-around Emulation Platforms may be developed to lower the cost of algorithm development and validation without expensive tools and compute CPU power/requirements
      • develops high-level system models usable by the client so as to proceed with development in parallel.(ie. Verilog/A high-level models)
      • Identifies where system-level specifications may need to be negotiated should they be unattainable. Generally system-level trade-offs are possible which may help with risk mitigation.

 

 

  • Deliverables Review and Acceptance Sign-off
    • Deliverables from the system study, as defined in the Statement of Work (SOW), is reviewed and signed off upon acceptance.
  • Development
    • Design effort required including schematic capture and simulation, the physical layout of the IC in addition to the verification effort needed to assure the specifications are being met under parasitic influences.
    • Emulation Prototype algorithms that are proven in the lab (inexpensively) are then ported for inclusion in the IC.
  • Design Review / Sign Off
    • Kaben conducts a design review with the client who defines the simulation tests and the resulting status of the simulation for specification conformance.
  • Feature Test Plan Development – in parallel to start of MPW Prototype Cycle
    • Occurs while the ICs are being fabricated.
    • Characterization boards designed, fabricated, and built
    • Software developed to drive characterization and testing. This may include automation for data acquisition purposes.
    • Production Test Development undertaken with our partners, working with their experts with a goal of achieving high fault coverage at low costs, effectively and efficiently.
    • Test Time Optimization
  • MPW / MLR  Prototype Cycle
    • This test-chip program makes use a multi-project wafer (MPW) or multi-layer reticle (MLR) services offered by our foundry partner.
    • IC is fabricated and packaged/assembled
    • IC is characterized against specification, any issues are identified and action taken to rectify.
    • Engineering or design changes made, re-fabricated using the MPW shuttle service and re-characterized if deemed necessary. If changes are minimal or low risk, it is generally an acceptable decision to move directly to high volume production full reticle sets (FRS) after minor modifications are made
    • After successfully meeting specifications, the results are reviewed against acceptance criteria and then signed off through the design review process.
    • Some key reliability tests may take place at this time such as ESD/latch-up testing.
  • Production
    • Full mask sets are then created based on the MPW results for mass production.
    • The ICs are assembled in the package
    • Production testing takes place on this packaged part
    • Production testing and supply management is handled through our supply management partner.

 

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