Kaben’s CTO, Tom Riley, at the Panel during IMS 2009, Boston, June 11th
"A Return to the Classic Heterodyne Architecture for Integrated Transceivers"

IMS (www.ims2009.org)  Panel Session

Thursday, June 11th, at 12:00-13:10, room 104ABC.

 
This Panel will feature our CTO, Mr. Tom Riley, who will share his experience with Kaben's on-chip tunable SIF filter technology and its application to reconfigurable transceivers. In addition, Tom will be available for meetings throughout the Conference. Please contact us if you would like to pre-arrange a meeting. 


A Return to the Classic Heterodyne Architecture for Integrated Transceivers?

Due to the inability to realize an integrated IF filter on a RF-IC, wireless transceivers have, over the past 15 years, generally adopted a Zero IF architecture.  Zero IF architectures avoid the need for an IF filter, but come with several undesirable features; such as DC offset (due to IP2), high 1/f noise level, and large ADC dynamic range and bandwidth.  Recently, new technologies have emerged that can allow high performance IF filters to be realized on-chip.  These advancements, in turn, can allow a return to the classic heterodyne architecture, with all of its advantages; robust adjacent channel blocking, high linearity, low noise, relaxed ADC dynamic range and bandwidth (reduced power consumption), and relaxed digital filtering (reduced latency).  On the other hand, the Zero IF architecture is now mature, and presents a significant barrier to a return to the classic heterodyne system.

This session will present opposing views on the viability of on-chip IF filters in volume production, and on the necessity (real or perceived) for such filters in standards applications.  The following topics will be addressed:

An overview of the advantages and limitations of both the heterodyne architecture and the Zero IF architecture

Realization of an on-chip heterodyne architecture using a novel Sampling IF filter

Realization of an on-chip heterodyne architecture using a novel MEMS IF filter

Advantages of the Low IF architectures (no on-chip IF filters)

Advantages of the Zero IF architectures (no on-chip IF filters)

Architectural challenges for high performance receivers

Although the Zero IF architecture has become pervasive, it has its difficulties with respect to performance in terms of blocker suppression, nonlinearity, DC offset, A/D performance, and digital filtering requirement.  A return to the heterodyne architecture has been made possible through recent novel, on-chip IF filter technologies.  Whether the industry will return to the robust heterodyne architecture, or remain with the now established Zero IF architecture is an open question.